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L6615
HIGH/LOW SIDE LOAD SHARE CONTROLLER
s s s s s s s
SSI SPECS COMPLIANT HIGH/LOW SIDE CURRENT SENSING FULLY COMPATIBLE WITH REMOTE OUTPUT VOLTAGE SENSING FULL DIFFERENTIAL LOW OFFSET CURRENT SENSE 2.7V TO 22V VCC OPERATING RANGE 32k SHARE SENSE AMPLIFIER INPUT IMPEDANCE HYSTERETIC UVLO
BCD TECHNOLOGY
DIP8 SO8 ORDERING NUMBERS: L6615N L6615D L6615DTR(T & Reel)
APPLICATION DISTRIBUTED POWER SYSTEMS s HIGH DENSITY DC-DC CONVERTERS s (N+1) REDUNDANT SYSTEMS, N UP TO 20 s SMPS FOR (WEB) SERVERS
s
DESCRIPTION This controller IC is specifically designed to TYPICAL APPLICATION DIAGRAM
RSENSE
+OUT +OUT_S -OUT_S -OUT
achieve load sharing of paralleled and independent power supply modules in distributed power systems, by adding only few external components. Current sharing is achieved through a single wire connection (share bus) common to all of the paralleled modules.
(*)
RADJ
PS #1
RG1
RG2
1 2 3 4
GND CSCS+ ADJ VCC CGA SHARE COMP
8 7 6 5
L6615
CC RC
RCGA
RSENSE
+OUT +OUT_S
(*)
RADJ +OUT LOAD GND
-OUT_S -OUT
PS #N
RG1
RG2
1 2 3 4
GND CSCS+ ADJ VCC CGA SHARE COMP
8 7 6 5
SHARE BUS
L6615
CC RC
RCGA
(*) OR-ing FET can be used to reduce power dissipation
July 2003
1/20
L6615
DESCRIPTION (continued) Load sharing is a technique used in all the systems in which the load requires low voltage, high current and/or redundancy; for this reason a modular power system is necessary in which two or more power supplies or DC-DC converters are paralleled. The device is able to perform both high side and low side current sensing, that is the sense current resistor can be placed either in series to the power supplies output or on the ground return. The L6615 then drives the share bus to a voltage proportional to the output current of the master that is to the highest amongst the output currents delivered by the paralleled power supplies. The share bus dynamics is independent of the power supply output voltage and is clamped only by the device supply voltage (VCC). The output voltage of the other paralleled power supplies (slaves) is then trimmed by the ADJ pin so that they can support their amount of load current. The slave power supplies work as current-controlled current sources. Sharing the output currents is useful for equalizing also the thermal stress of the different modules and providing an advantage in term of reliability. Moreover the paralleled supplies architecture allows achieving redundancy; the failure of one of the modules can be tolerated until the capability of the remaining power supplies is enough to provide the required load current. PIN DESCRIPTION
N 1 2 3 Pin GND CSCS+ Ground. Input of current sense amplifier; it is connected to the negative side of the sense resistor through a resistor (RG2). Input of current sense amplifier. A resistor (RG1, of the same value as RG2) is placed between this pin and the positive side of the sense resistor: its value defines the transconductance gain between ICGA and VSENSE. Output of Adjust amplifier; it is connected to both the load (through a resistor RADJ) and to the positive remote sense pin of the power system. This pin is an open collector diverting (from the feedback path) a current proportional to the difference between the current supplied to the load by the relevant power supply and the current supplied by the master. Output of the current sharing (transconductance) error amplifier and input of ADJ amplifier. Typically, a compensation network is placed between this pin and ground. The maximum voltage is internally clamped to 1.5V (typ.) Share bus pin. During the power supply slave operation, this pin acts as positive input from share bus. During power supply master operation, it drives the share bus to a voltage proportional to the load current. The share bus connects the SH pins of all the paralleled modules. A capacitor between this pin and GND could be useful to reduce the noise present on the share bus. Current Gain Adjust pin; current sense amplifier output. A resistor connected between this pin and ground defines the maximum voltage on the share bus and sets the gain of the current sharing system. Supply voltage of the IC. Function
4
ADJ
5
COMP
6
SH
7
CGA
8
VCC
2/20
L6615
ABSOLUTE MAXIMUM RATINGS
Symbol VCC ICS+, ICSVCS-, VCS+, VSH, VADJ, VCGA VCOMP (VCS+) - (VCS-) Ptot 2, 3, 6, 4, 7 Pin 8 Parameter Supply Voltage (*) (ICC<50mA) Sense pin current Value selflimit 10 -0.3 to VCC Error amplifier output Differential input voltage (VCS+ from 0V to 22V) Total power dissipation @ Tamb = 70C SO8 DIP8 Tj Tstg Junction temperature range Storage temperature 0.45 0.6 -40 to +125 -55 to +150 W C C -0.3 to 1.5 -0.7 to 0.7 Unit V mA V
5
V V
All voltages are with respect to pin 1. Currents are positive into, negative out of the specified terminal. (*) Maximum package power dissipation limits must be observed
PIN CONNECTION
GND 1 CS- 2 CS+ 3 ADJ 4
8 VCC 7 CGA 6 SH 5 COMP
THERMAL DATA
Symbol Rth j-amb Parameter Thermal Resistance junction to ambient MINIDIP 90 SO8 120 Unit C/W
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L6615
ELECTRICAL CHARACTERISTCS (Tj = -40 to 85C, Vcc=12V, VADJ = 12V, CCOMP = 5nF to GND, RCGA = 16k, unless otherwise specified; VSENSE = IL * RSENSE, RG1 = RG2 = 200)
Symbol Parameter Test Condition Min. Typ. Max. Unit
Vcc
Vcc Icc VCC, ON VCC,OFF VH Vz Operating range Quiescent current Turn-on voltage Turn-off voltage Hysteresis ICC = 20mA 0.1V VSH 10.0V VSENSE = 0.25V VCGA= 0V, VSENSE= 0.45V VSENSE = 0V, VCS+=+12V VSENSE = 0V, VCS+=0V VCS-, VCS+ VCS+ 0 1.6 0.16 24 VSH= 1V, VSENSE= 0V VSH= 0.2V, VSENSE= 0V 2.45 2.35 2.7 5 2.60 2.5 100 26 22 6 2.75 2.65 V mA V V mV V
CURRENT SENSE AMPLIFIER
VOS VCGA ICGAS IB(CS-) IB(CS+) CMR VTHCS+ SWH Input offset voltage Out high voltage Short circuit current Input bias current (high side sensing) Input bias current (low side sensing) Common mode dynamics range Switchover threshold low side to high side sensing Switchover hysteresis -1.5 Vcc-2.2 -1.5 -2.0 1.0 -1.0 VCC 0.0 1.5 mV V mA A A V V V
SHARE DRIVE AMPLIFIER
HVSH LVSH (+) (-) VSH, load ISC SR SH high output voltage SH low output voltage High side sensing mirror accuracy (*) Low side sensing mirror accuracy (*) Load regulation Short circuit current Slew rate -1.0mA ISDA(OUT) -4mA VSH= 0V, VSENSE= 25mV VSENSE= -10mV to 90mV step, RSH= 200 to GND VSENSE= 90mV to -10mV step, RSH= 200 to GND -20 0.8 2 -13.5 1.5 3 VSENSE= 250mV, ISH= -1mA VCGA= 0mV, RSH= 200 1 1 Vcc-2.2 45 5 5 20 -8 2.2 4 V mV % % mV mA V/s V/s
SHARE SENSE AMPLIFIER
Ri Input impedance 22.4 32 41.6 k
ERROR AMPLIFIER
Gm Vos Transconductance Input offset voltage VCGA=1V 3 30 4 50 5 70 mS mV
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L6615
ELECTRICAL CHARACTERISTCS (continued) (Tj = -40 to 85C, Vcc=12V, VADJ = 12V, CCOMP = 5nF to GND, RCGA = 16k, unless otherwise specified; VSENSE = IL * RSENSE, RG1 = RG2 = 200)
Symbol IOH IOL VCOMP(L) VZ Parameter Source current Sink current Low voltage Clamp Zener voltage IZ = 1mA Test Condition VCOMP=1.5V, V SH 300mV, VSENSE=-10mV VCOMP= 1.5V, VSENSE=-10mV 200 resistor SH to GND Min. -150 100 0.05 Typ. -350 200 0.15 1.5 Max. -400 300 0.25 V Unit A A
ADJ AMPLIFIER
IADJ VT RA Max. ADJ output current Threshold voltage Emitter resistor VSH= 1V, VSENSE= 0V IADJ=10A Guaranteed by design IADJ=5mA IADJ=1mA

6.5
10 0.7
13
mA V
60
100
140 1 0.4
V V
VADJ(MIN) Low saturation voltage
SH (*) Mirror accuracy is defined as = ----------------------------------------- - 1 100 :
V
RCG A V SE NSE -------------RG
and it represents the accuracy of the transfer between the voltage sensed and the voltage imposed on the share bus. BLOCK DIAGRAM
CS+ ICGA CGA 7
CURRENT SENSE AMPLIFIER (CSA) UVLO BIAS R R R R
3
2
CS8 24V VCC
+ _
6
R R
SH
SHARE SENSE AMPLIFIER (SSA) R
+ _
R
_ +
SHARE DRIVE AMPLIFIER (SDA)
+ _ ADJ 4 40 mV + _ RA
ADJ OUTPUT AMPLIFIER (AOA)
5 COMP
Gm ERROR AMPLIFIER (E/A)
1.5V 0.7V
1
GND
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L6615
Figure 1. Turn-on and turn-off voltage
VCC(ON), VCC(OFF) [V]
3
Figure 4. Max CGA current
ICGA(max) [mA]
2.8
2.6
2.4
2.6
2.2
2
2.2 -50 0 50 100
1.8 - 50 0 50 100
O
TJ [ C]
O
TJ [ C]
Figure 2. Supply current vs. supply voltage
ICC [ mA]
Figure 5. High side/low side sensing switchover threshold
VTH [V]
1.9
100
10
1.7
1
1.5
0.1
0.01 0.1 1
VCC [V]
1.3
10
100
- 50
0
50
100
TJ [ C]
O
Figure 3. Supply current
ICC [mA]
Figure 6. Max. share bus voltage at no load
VSH(LOW) [mV]
50 45
4.7
4.3
40
3.9
35 30
3.5
25 20
3.1
15
2.7 - 50 0
TJ [ C]
O
10
50
100
- 50
0
50
100
TJ [ C]
O
)
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L6615
Figure 7. Share bus input impedance
RI [k ]
Figure 8. ADJ maximum current
IAD J[MAX] [mA]
15
50
45
13
40
11
35
9
30
7
25
20 - 50 0
TJ [ C]
O
5
50
100
- 50
0
50
100
TJ [ C]
O
7/20
L6615
APPLICATION INFORMATION Index 1. 2. 3. 4. 5. 6. 7. 8. Introduction Current sense section Share drive section, error amplifier and adjust amplifier Designing with L6615 Current sense methods Application ideas Low voltage buses Offset Trimming page 8 9 10 10 13 14 15 16
1 INTRODUCTION Power supply systems are often designed by paralleling converters in order to improve performance and reliability. To ensure uniform distribution of stresses, the total load current should be shared appropriately among the converters. A typical application is showed in fig. 9 for a series of N paralleled modules (PS#1 to PS#N): each of them exhibits 4 terminals: two for the power output (+OUT, -OUT) and two for the remote sense signals (+OUT_S, -OUT_S). On the power lines are placed the sense resistors RSENSE (for the current sensing) and the OR-ing diodes (to avoid that the failure of one module shorts the load out) L6615 allows attaining an automatic master-slave current sharing architecture: one L6615 is associated to each power supply and all these IC's are linked each other through the share bus (referred to the common ground). This kind of system configuration is preferred to the systems in which a single current sharing controller is used because of robustness, reliability and flexibility. To configure a load share controller, few passive components are used. A brief device explanation will follow with the formulas useful to set these external components. Figure 9. Typical high side connection
RSENSE
+OUT +OUT_S -OUT_S -OUT
RADJ
PS #1
RG1
RG2
1 2 3 4
GND CSCS+ ADJ VCC CGA SHARE COMP
8 7 6 5
L6615
CC RC
RCGA
RSENSE
+OUT +OUT_S
RADJ
-OUT_S -OUT
+OUT LOAD GND
PS #N
RG1
RG2
1 2 3 4
GND CSCS+ ADJ VCC CGA SHARE COMP
8 7 6 5
SHARE BUS
L6615
CC RC
RCGA
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L6615
2 CURRENT SENSE SECTION A sense resistor is typically used to generate the voltage drop, proportional to the load current, measured by the CSA (Current Sense Amplifier), whose input pins (pins #2 and #3) are connected across of RSENSE through two identical resistors (RG1 and RG2). The CSA consists of 2 sections (see fig. 10), one responsible for the high side sensing, the other for low side sensing. An internal comparator activates the relevant section in accordance with the voltage present at CS+ pin: if this voltage is higher than 1.6V (typ), then the high side sensing section will be activated (fig10.a) otherwise the low side sensing one will (fig 10.b). For the sake of simplicity we will consider RG1= RG2= RG. As the voltage drop IOUT*R SENSE is present at the input of the Sense Amplifier section, its output forces the controlled current mirror to: - sink current from the CS+ pin in case of high side sensing (neglecting input bias current, no current flows through CS- pin); - source current from the CS- pin in case of low side sensing (neglecting input bias current, no current flows through CS- pin). The local feedback imposes the same voltage at the current sense input pins, so under closed loop condition VSENSE=VRG. The current
I OUT R S ENSE ICS = -------------------------------------RG
(ICS+ in case of high side, ICS- in case of low side) is then internally mirrored and sent to the CGA pin causing a drop across the R CGA external resistor: two internal buffers transfer VCGA signal on the share pin so: V SNS V SH = -------------- R CGA RG
Only the L6615 VCC limits the upper voltage at the CGA and SH pin, independently of the voltage present at the current sense pins. In noisy applications, two capacitors of small value (e.g. 1nF) connected between current sense pins and ground could be useful to clean the signal at the input of the current sense amplifier. For low voltage buses application, see paragraph 7. Figure 10. Current sense section
PS+
RG + CS+ IOUT VRG
LOAD(-) / GND
ICS+ RG
SINK
CSA
+ CS+ IOUT ICGA RSENSE CGA RCGA VSENSE
1.6V COMPARE CONTROLLED CURRENT MIRROR
-
HSA
1:1
CONTROLLED CURRENT MIRROR
-
HSA
RSENSE
VSENSE
1.6V
COMPARE
CGA ICGA RCGA
CSRG LSA +
VRG CS-
LSA +
1:1
SOURCE
CSA PSL6615
RG
ICS-
LOAD(+)
L6615
a) high side sensing
b) low side sensing
9/20
L6615
3 SHARE DRIVE SECTION, ERROR AMPLIFIER AND ADJUST AMPLIFIER The gain between the output of CSA (CGA pin) and output of SDA (SH pin) is 1 (typ.) so, for the master power supply, VCGA = VSH; the voltage on the share bus is imposed by the master. In the slave converters, being VCGA(SLAVE) < VCGA(MASTER), the diode at the output of SDA (see block diagram) isolates the output this amplifier from the share bus. The Share Sense Amplifier (SSA) reads the bus voltage transferring the signal to the non-inverting input of the error amplifier where it is compared with CGA voltage. Whenever a controller acts as the master in the system, the voltage difference between the E/A inputs is zero. To guarantee its output low in such condition, a 40mV offset is inserted in series with the inverting input. Instead in the slave converters the input voltage difference is proportional to the difference between the master load current and the relevant slave load current. The transconductance E/A converts the V at its inputs in a current equal to
IO UT = G M V
flowing in the compensation network connected between COMP pin and ground. The E/A output voltage drives the adjust amplifier to sink current from the ADJ pin that is connected to the output voltage through a small resistor along the sense path. The current sunk by ADJ pin is deviated from feedback path of the slave power supply that reacts increasing its duty cycle. In steady state the current sunk by the ADJ pin is proportional to the value of error amplifier output. 4 DESIGNING WITH L6615 The first design step is usually the choice of the sense resistor whose maximum value is limited by power dissipation; this constraint must be traded off against the precision of L6615 current sensing. In fact a small sense resistance value lowers the power dissipation but reduces the signal available at the inputs of the L6615 current sense amplifier. Once fixed RSENSE then the values for R G and RGCA will be chosen in accordance with the application specs: usually these specs define the share bus voltage (VSH(MAX)) and the number of paralleled power supplies. Their value must comply with the constraints imposed by the L6615: Figure 11. Simplified feedback block diagram.
IOUT(1) POWER STAGE 1 RSENSE ZL
ILOAD
VOUT
IOUT(2) RSENSE POWER STAGE 2
PWM CONTROLLER
* RCGA / RG
SHARE BUS
* RCGA / RG
PWM CONTROLLER
+ + K*VOUT (*)
GM*ZCOMP(s)*RADJ RA
+
+
GM*ZCOMP(s)*RADJ RA
VREF
+ -
+
VREF
(*) K depends on the feedback divider ratio
K*VOUT (*)
10/20
L6615
- maximum share bus voltage is internally limited up to 2.2V below L6615 VCC voltage (pin#8); - VSH(MAX) represents an upper limit but the designer should select the full scale share bus voltage keeping in mind that every Volt on the share bus will increase the master controller's supply current by approximately 45A for each slave unit connected in parallel; this total current, provided by the master share drive amplifier, must be lower than its minimum output capabilty (8mA) so R i ( MIN ) V SH ( MA X ) < ------------------ 8mA N This condition is not tough to meet in normal applications, as one can easily see by using sensible values for N (number of paralleled power supplies) and VSH(MAX). For example, with VSH(MAX)=8V, solving for N, we obtain Nmax=20; - maximum share drive amplifier current capability (ICGA(MAX)=2mA); - for safety reasons the following relation must be met:

V out 1 R G > -- --------------- - 40 2 10mA

in this way no fault will cause ICS+ (or ICS-) to overcome its absolute maximum ratings. At full load, VSENSE(MAX) = IOUT(MAX) * RSENSE(MAX) is the maximum voltage drop across the resistor RSENSE (typically few hundreds of millivolt). IOUT(MAX) is the maximum current carried by each of the paralleled power supply; in non redundant systems composed by N power supplies, each of them works at its nominal current, so: I LOAD I OUT ( MAX ) = --------------N This relationship is true also in N+M redundant system, even if under normal condition each power supply provides ILOAD/(N+M). For example in a system composed by two paralleled power supplies 100% redundant (N=M=1), each module is sized to sustain the entire load current (in normal operation it carries only one half): for this reason the sense resistor must be sized considering the whole load current. The temperature variation of the sense resistor (hence of its resistance value) has to be taken into account, so RSENSE(MAX) is the value at maximum operating temperature to avoid saturating the share bus. Once fixed VSENSE(MAX), the ratio RCGA/RG (gain from the sensing section to the share bus) can be calculated: R CGA V SH ( MAX ) --------------- = ------------------------------------RG V SENSE ( MAX ) where VSH(MAX) is defined by the application. A small capacitor in parallel to R CGA is useful to reduce the noise. The effect of current sharing feedback loop is to force the voltages of the slave's CGA pins to be equal to VSH (that is to reduce the voltage difference at the inputs of the L6615 error amplifier). For the sake of simplicity we consider 2 paralleled power supplies (as in fig. 11): under closed loop condition: R SNS ( 1 ) R SNS ( 2 ) I OUT ( 1 ) --------------------- R CGA ( 1 ) = I OUT ( 2 ) --------------------- R CGA ( 2 ) RG ( 1 ) RG( 2) Ideally all the external component and are matched so: I LOAD I OUT ( 1 ) = I OUT ( 2 ) = --------------2 Any mismatch will have repercussion on the sharing precision: in particular the maximum difference between the output currents (sharing error) will be given by the sum of the mismatches amongst the relevant values.
11/20
L6615
Figure 12. ADJ network
VOUT RADJ VOUT RADJ IADJ to L6615 ADJ pin
IADJ to L6615 ADJ pin Off the shelf POWER SUPPLY E/A R2
R1 E/A VREF
VREF
a)
b)
To set the RADJ value it is necessary to know the tolerance required of the power supply output voltage (VOUTVO); the maximum difference between master and slave output voltage is 2*VO and this amount represents the voltage that the L6615 must be able to correct. Now two different approaches are feasible depending on whether the SMPS (whose output current must be shared) has to be completely designed or it is an "off the shelf" component and only the current sharing section must be designed. In the first case, the adjustment resistor (RADJ) can be considered as a fraction of the high resistor of the feedback divider RH (see fig.12.a): typically the first step consist of fixing the current flowing, under steady state condition, through the feedback divider IFB; by choosing the value for R2: V REF I FB = ------------R2 we will have: V OUT -------------- - 1 R 2 V REF It can be an useful rule of thumb to use RADJ lower than (or equal to) one tenth of R1, considering that, in worst case condition, it will be: V OUT I ADJ ( max ) = -----------------R ADJ R H = R 1 + R ADJ = This value must not exceed the one indicated in the "Electrical characteristic section" but this is very easy to meet, as one can easily see by using sensible values for VOUT and R 2. In the second case (fig 12.b), the feedback divider has been already designed by the SMPS manufacturer and it is not possible to modify it: the design of RADJ must be done to make the L6615 able to correct the maximum spread without significantly shifting the SMPS regulation point. A minimum RADJ value can be found by: V OUT R ADJ ( min ) = ------------------------I ADJ ( max ) where IADJ(max) is 8mA. Especially for low voltage output buses it is important to avoid adjustment network saturation; the design must satisfy the following relationship: V OUT - R ADJ ( I ADJ + I FB ) > V A DJ( MIN ) where VADJ(MIN) can be found in the "Electrical characteristic section" for different IADJ values.
12/20

L6615
The last point is the design of the compensation network ZC(s) connected between the COMP pin and ground. Besides the power supply feedback loop, the current sharing system introduces another, outer loop. To avoid interaction between them it is important to design the bandwidth of the sharing loop at least one order of magnitude lower than the bandwidth of the power supply loop. For the total system, the loop gain is: R CGA R ADJ 1 G LOOP ( s ) = R SENSE --------------- G M Z C ( s ) ------------- A PWR ( s ) -----------------R R R
G A
LOA D
where APWR(s) is the transfer function of PWM controller and power stage (see fig. 11) RLOAD is the equivalent load resistance Typically the compensation network is built by a R-C series. A resistor in series with CC is required to boost the phase margin of the load share loop. The zero is placed at the load share loop crossover frequency, fC(SH). If fC(SH) is the share loop crossover frequency, then: R CGA G M R ADJ R SENSE 1 C C = ------------------------------- ---------------------------- ------------- --------------------- A PWR ( f RA R LOAD 2 f C ( SH ) RG C ( SH ) ) 1 R C = -------------------------------------------2 f C ( SH ) C C 5 CURRENT SENSE METHODS Several are the methods to sense the power supply output current; the simplest one is to use a power resistor (fig. 13a) but increasing load current could require expensive resistor to support the inherent power dissipation, imposing the use of several paralleled resistor. Other methods to sense the output current are showed in fig. 13b and 13c: 1. RDS(ON): a power MOS is placed in series to the output and its channel resistance (RDS(ON)) is used as sense resistor (fig 13a): the L6615 sense pins will be connected, through RG resistors to the drain and to the source of the MOS. Besides providing the sense resistor, the FET is used as "ORing" element: driving properly its gate, it is possible isolate the power supply output from the load (the body diode is reversed biased so it doesn't conduct). This is useful whenever features like hot swap or hot plug are required; compared with the well-known solution using ORing diode, the ORing FET greatly reduces the power dissipation, in particular:
P ( DIO DE ) = VF IOUT + R SE NSE IOUT P( MOS ) = R DS ( O N ) I OUT
2 2
where VF is the forward drop across the diode. 2. Current transformer: in case of very high load currents, a transformer allows sensing a smaller current, obtained through a scaling factor equal to the transformer turn ratio. In this way, the sense resistor power dissipation requirements can be less tight: obviously this is paid with the cost of the transformer. In fig. 13c it is showed the simplified output stage of a power supply in forward configuration: through two current transformers the load current is reproduced in the sensing circuit scaled by a factor N. RSENSE will read a ripple (at the switching frequency) superimposed on the average current value that doesn't affect the correct behaviour of the current sharing system because its loop gain is designed with a low bandwidth - at least 2 order of magnitude lower than the switching frequency - that will cut this high frequency.
13/20
L6615
Figure 13. Current sense methods.
CS+ RG
L6615
CSRG
CS+ RG
L6615
RG
CS+
CSRG 1:N 1:N
RSNS RG
CS-
L6615
ORing FET
RSNS IOUT POWER SUPPLY L O A D IOUT POWER SUPPLY GATE CONTROL L O A D
IOUT
SENSING CIRCUIT
L O A D
a)
b)
c)
6 APPLICATION IDEAS In fig. 14 is showed a single section of a system in which several DC to DC modules can be paralleled, typical solution whenever the load requires high current at low voltage; the converter is designed for a step down configuration using a synchronous rectification controller (for example L6910 [1] or L6911 [2] ST device). The L6615 reads the drop across the Rds(ON) of the OR-ing FET and the LM293 drives its gate, pulling it down whenever a fault condition (e.g. short on the low side) appears. A charge pump could be necessary to be sure that the ORing FET VGS is higher than VGS(TH) (depending on the input and output voltage). Figure 14. 0.9 to 5V DC-Dc converter with Current Sharing and output hot-pluggability
VIN
8 5
BOOT UGATE VCC PHASE GND LGATE SS PGND
4
LM293
7 6
VOUT
CS+ ADJ VIN GND
CSVcc
+S_OUT
L6910
COMP VFB
L6615
CGA
COMP
SH
SH
R1
Q1
-SOUT
P_GND
14/20
L6615
Figure 15. Distributed power system for +48V bus
+48V
+48V (*) feedback
IOUT1 RSNS
AC Mains
L O A D
IOUT2 RSNS
+48V GND +12V
RG
RG
RG
RG
DPS1
(*) the center of the output feedback divider is usually connected to a voltage compatible with L6615 AMR
CSADJ Vcc
CS+ SH GND
SH bus
CS+ SH GND
CSADJ Vcc
L6615
L6615
In this application is inserted also a circuit for the square current limit protection in case of overcurrent (R1Q1): being the voltage at the CGA pin directly proportional to the current carried by the relevant section, it is possible to set the CGA resistor such that, until the output current is in the right range, the CGA voltage is lower than VREF+0.7. As soon as this value is overcome, then the bipolar pushes current in the feedback path, reducing the duty cycle and consequently the output voltage. Current sharing can be required in AC to DC application like distributed power system (DPS) for telecom applications: if the output voltage is higher than the absolute maximum rating for the current sense pins (CS+ and CS-) high side sensing can not be performed unless adding other components; the current sense is performed on the ground return. To maintain high side sensing two resistor dividers (between the edge of R SENSE and ground) could be introduced to translate the sense signal in the L6615 input pin common mode range. In fig.15 two AC-DC converters supply the same load through a +48V bus; these converters usually exhibit also a +12V auxiliary output useful to supply the L6615 whose ADJ pin works on the +48V feedback section (COMP pin and CGA pin connections are not showed) in figure 15. 7 LOW VOLTAGE BUSES The L6615 has a "doubled" sense structure, designed to perform both high side and low side sensing: the first solution is usually considered more convenient. Actually low side sensing means to split the ground return as many times as the power supplies paralleled are: on each of these paths it is then necessary to place the sense resistor introducing a drop between the power supply ground and the common load negative reference. The voltage at CS+ pin is read by an internal comparator and compared with a reference corresponding to the switchover threshold VTHcs+ whose value is typically 1.6V. If such value is overcome, then the comparator triggers the High Side Amplifier (HSA); being the threshold provided by hysteresis, then the Low Side Amplifier (LSA) will be triggered as VCS+ is lower than 1.44V (typ.). Hence VTHcs+ defines the threshold between the operating range of LSA, (referring to fig.10) and the operating range of HSA; usually LSA is operating when the sense resistor is placed on the ground return, between the negative load terminal and the negative power supply output (fig 10.b) and HSA when the sense resistor is placed between the power supply positive output and the load. It is however possible to perform high side sensing for applications whose output voltage is close to VTHcs+ threshold (or even lower) exploiting the low sense internal structure (LSA).
00000000000000000000000000000 000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000
+48V
+48V (*) feedback
000000000000000000000000000 00000000000000000000000000000000000000000000000000000 0000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000
AC Mains
+48V GND +12V
DPS2
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L6615
Consider, for example an application with VOUT = 1.2V and the sense resistor placed high side; the voltage at CS+: VCS+ = VOUT - VSENSE is lower than 1.6V so the internal comparator triggers on the LSA structure and the pin CS- sources the current ICS (see paragraph "2. CURRENT SENSE SECTION"). The IC works properly because the dynamics of LSA spreads down to zero: in this case it is necessary to pay attention to the design of ADJ network. Now consider, for example, an application with VOUT =1.5V where, because of the drop across RSNS, the voltage at CS+ pin could be very close to the threshold: if such voltage is overcome (start-up, load regulation, overvoltage,...) , then the HSA structure will be activated; as nominal conditions are restored, the hysteresis will then keep HSA active (unless VCS+ falls under the lower threshold). 8 OFFSET TRIMMING The current sharing accuracy strongly depends on the unbalance between the relevant parameters of the paralleled sections. Each percentage point on the relevant parameters tolerance introduces a maximum error equal to the double of the tolerance.The L6615 introduces an inherent error in current sharing due to the 40mV offset at the negative input of the error amplifier; this offset is necessary to guarantee the low value of the master COMP pin. Considering perfectly matched all other parameters, the offset introduces a percentage error equal to 4% divided by the voltage on the share bus. In particular:

40mA I SLAV E = I MAST ER 1 - --------------VS H

Being VSH directly proportional to the load current and fixed the ratio R CGA/RG, higher are the currents involved in the sharing, lower is the error. Another error is introduced by the current sense amplifier due to its input offset whose amplitude can be 1mV: being typically the drop across RSNS about one hundred mV at full load, the offset could lead to an error of some percentage point. Whenever the application requires very high current sharing accuracy, it is possible to correct these offsets through a triggering process, introducing a trimmer (RK) between current sense input pins. Referring to fig. 16, in case of high side sensing, the equations governing the circuit are: V OUT - V M VM ---------------------------- = ---------------------------( 1 - ) RK RG V OUT + V SENSE - V P VP -------------------------------------------------------- - -------------- = I G RK RG VP = VM + VO where VO is the current sense amplifier input offset. Solving for IG, we get: V SENSE R K + R G 2-1 I G = --------------------- - ----------------------------- V O + V OUT ------------------------------------------------------ [ RK ( 1 - ) + R G ] R K RG RG Ideally IG should be equal only to the first term: this current will be sunk by CS+ pin, internally mirrored with 1:1 ratio and sent to CGA pin. Imposing that the sum of two latter terms is zero it is possible to find the value of deleting the effect of the offset: 1 2 V OUT R G - 4 V OUT R G + V O R K + 4 V O R G R K OPT = -- - ----------------------------------------------------------------------------------------------------------------------------------------------------------2 2 VO RK
2 2 2 2 2
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Figure 16. Offset Trimming
ILOAD VOUT+VSENSE + RSNS RG RG _
VOUT
RK IG VP CS+ CGA RCGA
(1-) RK VM CS-
L6615
Because of the tolerance of the output voltage, it is not possible to delete completely the effect of the offset on CGA pin on all the allowed output voltage range: if the trimming operation is performed at VOUT(MIN), then on pin CGA the maximum residual voltage will be present at VOUT(MAX) and its value will be: 1 - 2 OPT R CGA ( V OUT (MAX ) - V OUT ( MIN ) ) --------------------------------------------------------------------------- OPT ( R K OPT - R K - R G ) To simplify the procedure, the following step-by step process can be used: s a trimmer has to be placed between sense pins of each section: the value of the trimmer resistance must be at least one order of magnitude higher than RG and it has to be set at one half of its range (=0.5); s once the application is running at a load defined by the designer based on the required sharing accuracy, the master section has to be located; s on the slave sections it is then necessary to operate on the trimmer to make equal the output currents. REFERENCE [1] "L6910 - Adjustable step down controller with synchronous rectification" (Datasheet) [2] "L6911 - 5 bit programmable step down controller with synchronous rectification" (Datasheet
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mm DIM. MIN. A a1 B b b1 D E e e3 e4 F I L Z 3.18 7.95 2.54 7.62 7.62 6.6 5.08 3.81 1.52 0.125 0.51 1.15 0.356 0.204 1.65 0.55 0.304 10.92 9.75 0.313 TYP. 3.32 0.020 0.045 0.014 0.008 MAX. MIN.
inch TYP. 0.131 MAX.
OUTLINE AND MECHANICAL DATA
0.065 0.022 0.012 0.430 0.384 0.100 0.300 0.300 0.260 0.200 0.150 0.060
Minidip
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DIM. MIN. A a1 a2 a3 b b1 C c1 D (1) E e e3 F (1) L M S 3.8 0.4 4.8 5.8 0.65 0.35 0.19 0.25 0.1
mm TYP. MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 0.026 0.014 0.007 0.010 0.004 MIN.
inch TYP. MAX. 0.069 0.010 0.065 0.033 0.019 0.010 0.020
OUTLINE AND MECHANICAL DATA
45 (typ.) 5.0 6.2 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.15 0.016 0.189 0.228 0.050 0.150 0.157 0.050 0.024 0.197 0.244
SO8
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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